硬件设计基础三实验报告

 `timescale 1ns/1ps

 module comp4(
 input wire [3:0] A,
 input wire [3:0] B,
 output wire       AGTB,
 output wire       AEQB,
 output wire       ALTB
 );
 assign AGTB = (A > B);
 assign AEQB = (A == B);
 assign ALTB = (A < B);
 endmodule

 module exp2_1_top(
 input wire [3:0] A,
 input wire [3:0] B,
 output wire       AGTB,
 output wire       AEQB,
 output wire       ALTB
 );
 comp4 u_comp4(.A(A), .B(B), .AGTB(AGTB), .AEQB(AEQB), .ALTB(ALTB));
 endmodule

 `timescale 1ns/1ps

 module comp8(
 input wire [7:0] A,
 input wire [7:0] B,
 output wire       AGTB,
 output wire       AEQB,
 output wire       ALTB
 );
 wire gt_h, eq_h, lt_h;
 wire gt_l, eq_l, lt_l;

 comp4 u_high(.A(A[7:4]), .B(B[7:4]), .AGTB(gt_h), .AEQB(eq_h), .ALTB(lt_h));
 comp4 u_low (.A(A[3:0]), .B(B[3:0]), .AGTB(gt_l), .AEQB(eq_l), .ALTB(lt_l));

 assign AGTB = gt_h | (eq_h & gt_l);
 assign AEQB = eq_h & eq_l;
 assign ALTB = lt_h | (eq_h & lt_l);
 endmodule

 module exp2_2_top(
 input wire [7:0] A,
 input wire [7:0] B,
 output wire       AGTB,
 output wire       AEQB,
 output wire       ALTB
 );
 comp8 u_comp8(.A(A), .B(B), .AGTB(AGTB), .AEQB(AEQB), .ALTB(ALTB));
 endmodule

 `timescale 1ns/1ps

 module full_adder(
 input wire A,
 input wire B,
 input wire Cin,
 output wire S,
 output wire Cout
 );
 assign S    = A ^ B ^ Cin;
 assign Cout = (A & B) | (A & Cin) | (B & Cin);
 endmodule

 module add8_serial_carry(
 input wire [7:0] A,
 input wire [7:0] B,
 input wire       Cin,
 output wire [7:0] S,
 output wire       Cout
 );
 wire [8:0] c;
 assign c[0] = Cin;
 assign Cout = c[8];

 full_adder u0(.A(A[0]), .B(B[0]), .Cin(c[0]), .S(S[0]), .Cout(c[1]));
 full_adder u1(.A(A[1]), .B(B[1]), .Cin(c[1]), .S(S[1]), .Cout(c[2]));
 full_adder u2(.A(A[2]), .B(B[2]), .Cin(c[2]), .S(S[2]), .Cout(c[3]));
 full_adder u3(.A(A[3]), .B(B[3]), .Cin(c[3]), .S(S[3]), .Cout(c[4]));
 full_adder u4(.A(A[4]), .B(B[4]), .Cin(c[4]), .S(S[4]), .Cout(c[5]));
 full_adder u5(.A(A[5]), .B(B[5]), .Cin(c[5]), .S(S[5]), .Cout(c[6]));
 full_adder u6(.A(A[6]), .B(B[6]), .Cin(c[6]), .S(S[6]), .Cout(c[7]));
 full_adder u7(.A(A[7]), .B(B[7]), .Cin(c[7]), .S(S[7]), .Cout(c[8]));
 endmodule

 module exp2_3_top(
 input wire [7:0] A,
 input wire [7:0] B,
 input wire       Cin,
 output wire [7:0] S,
 output wire       Cout
 );
 add8_serial_carry u_add8(.A(A), .B(B), .Cin(Cin), .S(S), .Cout(Cout));
 endmodule

 `timescale 1ns/1ps

 module jk_ff(
 input wire clk,
 input wire rst_n,
 input wire J,
 input wire K,
 output reg  Q
 );
 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) Q <= 1'b0;
 else begin
 case ({J, K})
 2'b00: Q <= Q;
 2'b01: Q <= 1'b0;
 2'b10: Q <= 1'b1;
 2'b11: Q <= ~Q;
 endcase
 end
 end
 endmodule

 module mod8_counter_jk(
 input wire clk,
 input wire rst_n,
 input wire en,
 output wire [2:0] Q
 );
 wire j0 = en;
 wire k0 = en;
 wire j1 = en & Q[0];
 wire k1 = en & Q[0];
 wire j2 = en & Q[1] & Q[0];
 wire k2 = en & Q[1] & Q[0];

 jk_ff u0(.clk(clk), .rst_n(rst_n), .J(j0), .K(k0), .Q(Q[0]));
 jk_ff u1(.clk(clk), .rst_n(rst_n), .J(j1), .K(k1), .Q(Q[1]));
 jk_ff u2(.clk(clk), .rst_n(rst_n), .J(j2), .K(k2), .Q(Q[2]));
 endmodule

 module divider_tick #(parameter integer CLK_FREQ = 100_000_000)(
 input wire clk,
 input wire rst_n,
 input wire [1:0] sw,
 output reg  tick
 );
 reg [31:0] cnt;
 reg [31:0] limit;

 always @(*) begin
 case (sw)
 2'b00: limit = CLK_FREQ;
 2'b01: limit = CLK_FREQ / 2;
 2'b10: limit = CLK_FREQ / 4;
 default: limit = CLK_FREQ / 8;
 endcase
 end

 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) begin
 cnt <= 32'd0; tick <= 1'b0;
 end else if (cnt >= limit - 1) begin
 cnt <= 32'd0; tick <= 1'b1;
 end else begin
 cnt <= cnt + 32'd1; tick <= 1'b0;
 end
 end
 endmodule

 module seg7_decimal(input wire [3:0] num, output reg [7:0] seg);
 always @(*) begin
 case (num)
 4'd0: seg = 8'b1100_0000; 4'd1: seg = 8'b1111_1001;
 4'd2: seg = 8'b1010_0100; 4'd3: seg = 8'b1011_0000;
 4'd4: seg = 8'b1001_1001; 4'd5: seg = 8'b1001_0010;
 4'd6: seg = 8'b1000_0010; 4'd7: seg = 8'b1111_1000;
 default: seg = 8'b1111_1111;
 endcase
 end
 endmodule

 module exp3_top #(parameter integer CLK_FREQ = 100_000_000)(
 input wire       clk,
 input wire       reset,
 input wire [1:0] sw,
 output wire [2:0] count,
 output wire [7:0] seg,
 output wire [7:0] an
 );
 wire rst_n = ~reset;
 wire tick;
 divider_tick #(.CLK_FREQ(CLK_FREQ)) u_div(.clk(clk), .rst_n(rst_n), .sw(sw), .tick(tick));
 mod8_counter_jk u_cnt(.clk(clk), .rst_n(rst_n), .en(tick), .Q(count));
 seg7_decimal u_seg(.num({1'b0, count}), .seg(seg));
 assign an = 8'b1111_1110;
 endmodule

 `timescale 1ns/1ps

 module fsm_tick #(parameter integer DIV = 25_000_000)(
 input wire clk,
 input wire rst_n,
 output reg  tick
 );
 reg [31:0] cnt;
 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) begin cnt <= 32'd0; tick <= 1'b0; end
 else if (cnt >= DIV - 1) begin cnt <= 32'd0; tick <= 1'b1; end
 else begin cnt <= cnt + 32'd1; tick <= 1'b0; end
 end
 endmodule

 module gray_flow_fsm(
 input wire clk,
 input wire rst_n,
 input wire tick,
 input wire dir,
 output reg  [7:0] led,
 output reg  [2:0] state
 );
 reg [2:0] next_state;

 always @(*) begin
 if (!dir) begin
 case (state)
 3'b000: next_state = 3'b001;
 3'b001: next_state = 3'b011;
 3'b011: next_state = 3'b010;
 3'b010: next_state = 3'b110;
 3'b110: next_state = 3'b111;
 3'b111: next_state = 3'b101;
 3'b101: next_state = 3'b100;
 default: next_state = 3'b000;
 endcase
 end else begin
 case (state)
 3'b000: next_state = 3'b100;
 3'b100: next_state = 3'b101;
 3'b101: next_state = 3'b111;
 3'b111: next_state = 3'b110;
 3'b110: next_state = 3'b010;
 3'b010: next_state = 3'b011;
 3'b011: next_state = 3'b001;
 default: next_state = 3'b000;
 endcase
 end
 end

 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) state <= 3'b000;
 else if (tick) state <= next_state;
 end

 always @(*) begin
 case (state)
 3'b000: led = 8'b0000_0001; 3'b001: led = 8'b0000_0010;
 3'b011: led = 8'b0000_0100; 3'b010: led = 8'b0000_1000;
 3'b110: led = 8'b0001_0000; 3'b111: led = 8'b0010_0000;
 3'b101: led = 8'b0100_0000; default: led = 8'b1000_0000;
 endcase
 end
 endmodule

 module onehot_flow_fsm(
 input wire clk,
 input wire rst_n,
 input wire tick,
 input wire dir,
 output reg  [7:0] led
 );
 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) led <= 8'b0000_0001;
 else if (tick) begin
 if (!dir) led <= {led[6:0], led[7]};
 else led <= {led[0], led[7:1]};
 end
 end
 endmodule

 module exp6_top #(parameter integer DIV = 25_000_000)(
 input wire       clk,
 input wire       reset,
 input wire       dir_sw,
 input wire       mode_sw,
 output wire [7:0] led,
 output wire [7:0] seg,
 output wire [7:0] an
 );
 wire rst_n = ~reset;
 wire tick;
 wire [7:0] led_gray, led_onehot;
 wire [2:0] gray_state;

 fsm_tick #(.DIV(DIV)) u_tick(.clk(clk), .rst_n(rst_n), .tick(tick));
 gray_flow_fsm u_gray(.clk(clk), .rst_n(rst_n), .tick(tick), .dir(dir_sw), .led(led_gray), .state(gray_state));
 onehot_flow_fsm u_onehot(.clk(clk), .rst_n(rst_n), .tick(tick), .dir(dir_sw), .led(led_onehot));

 assign led = mode_sw ? led_onehot : led_gray;
 assign seg = 8'b1111_1111;
 assign an  = 8'b1111_1111;
 endmodule

 `timescale 1ns/1ps

 module clock_top #(
 parameter integer CLK_FREQ = 100_000_000,
 parameter integer FAST_HZ  = 100
 )(
 input wire       clk,
 input wire       reset,
 input wire       fast_sw,
 output reg  [7:0] seg,
 output reg  [7:0] an
 );
 wire rst_n = ~reset;

 reg [31:0] tick_cnt;
 reg tick_1s;
 wire [31:0] tick_limit = fast_sw ? (CLK_FREQ / FAST_HZ) : CLK_FREQ;

 // 计时脉冲：正常 1Hz，加速模式 FAST_HZ
 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) begin
 tick_cnt <= 32'd0;
 tick_1s <= 1'b0;
 end else if (tick_cnt >= tick_limit - 1) begin
 tick_cnt <= 32'd0;
 tick_1s <= 1'b1;
 end else begin
 tick_cnt <= tick_cnt + 32'd1;
 tick_1s <= 1'b0;
 end
 end

 reg [3:0] sec_u, sec_t;
 reg [3:0] min_u, min_t;
 reg [3:0] hour_u, hour_t;

 // BCD 计数：HH:MM:SS，范围 00:00:00 ~ 23:59:59
 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) begin
 sec_u <= 4'd0; sec_t  <= 4'd0;
 min_u <= 4'd0; min_t  <= 4'd0;
 hour_u <= 4'd0; hour_t <= 4'd0;
 end else if (tick_1s) begin
 if (sec_u != 4'd9) begin
 sec_u <= sec_u + 4'd1;
 end else begin
 sec_u <= 4'd0;
 if (sec_t != 4'd5) begin
 sec_t <= sec_t + 4'd1;
 end else begin
 sec_t <= 4'd0;
 if (min_u != 4'd9) begin
 min_u <= min_u + 4'd1;
 end else begin
 min_u <= 4'd0;
 if (min_t != 4'd5) begin
 min_t <= min_t + 4'd1;
 end else begin
 min_t <= 4'd0;
 if (hour_t == 4'd2 && hour_u == 4'd3) begin
 hour_t <= 4'd0; hour_u <= 4'd0;
 end else if (hour_u != 4'd9) begin
 hour_u <= hour_u + 4'd1;
 end else begin
 hour_u <= 4'd0; hour_t <= hour_t + 4'd1;
 end
 end
 end
 end
 end
 end
 end

 // 动态扫描分频，约 1 kHz 以上即可稳定显示
 reg [16:0] scan_cnt;
 reg [2:0]  scan_sel;
 always @(posedge clk or negedge rst_n) begin
 if (!rst_n) begin
 scan_cnt <= 17'd0;
 scan_sel <= 3'd0;
 end else if (scan_cnt >= CLK_FREQ / 8000 - 1) begin
 scan_cnt <= 17'd0;
 scan_sel <= scan_sel + 3'd1;
 end else begin
 scan_cnt <= scan_cnt + 17'd1;
 end
 end

 reg [3:0] cur_digit;
 always @(*) begin
 an = 8'b1111_1111;
 case (scan_sel)
 3'd0: begin an = 8'b1111_1110; cur_digit = sec_u;  end
 3'd1: begin an = 8'b1111_1101; cur_digit = sec_t;  end
 3'd2: begin an = 8'b1111_1011; cur_digit = min_u;  end
 3'd3: begin an = 8'b1111_0111; cur_digit = min_t;  end
 3'd4: begin an = 8'b1110_1111; cur_digit = hour_u; end
 3'd5: begin an = 8'b1101_1111; cur_digit = hour_t; end
 default: begin an = 8'b1111_1111; cur_digit = 4'd0; end
 endcase
 end

 always @(*) begin
 case (cur_digit)
 4'd0: seg = 8'b1100_0000;
 4'd1: seg = 8'b1111_1001;
 4'd2: seg = 8'b1010_0100;
 4'd3: seg = 8'b1011_0000;
 4'd4: seg = 8'b1001_1001;
 4'd5: seg = 8'b1001_0010;
 4'd6: seg = 8'b1000_0010;
 4'd7: seg = 8'b1111_1000;
 4'd8: seg = 8'b1000_0000;
 4'd9: seg = 8'b1001_0000;
 default: seg = 8'b1111_1111;
 endcase
 end
 endmodule